A particular process step in the manufacturing of integrated circuits, devices, and packages involves plating a semiconductor wafer or workpiece (e.g., flat panel, magnetic recording heads, packages, etc.) surface with a conductive material. Plating the wafer or workpiece surface with the conductive material has important and broad application in the semiconductor industry.
FIG. 1 illustrates a cross sectional view of a substrate with topographical features having various layers disposed thereon. For example, this figure illustrates a substrate 2 with or without devices (i.e., transistors, etc.) having deposited thereon a barrier or adhesive layer 4 and a seed layer 6. The top surface of the substrate 2 may be patterned with vias, trenches, holes, and other features, or it may be flat. The barrier layer 4 may be tantalum (Ta), nitrides of tantalum (Ta), titanium (Ti), tungsten, TiW, CuWP, CoWP or combinations of any other material that is commonly used in this field. The barrier layer 4 is generally deposited on the substrate 2 by any of the various sputtering methods, by chemical vapor deposition (CVD), or by electrolyte/electroless plating methods. Thereafter, the seed layer 6 is deposited over the barrier layer 4.
The barrier layer 4 and the seed layer 6 may also be formed on the substrate 2 by using an electro-deposition method. This method offers distinct and unique advantages of lower costs and beneficial material properties (i.e., low stress in the substrate 2) as opposed to using other deposition methods.
The seed layer 6 material may be copper or copper substitutes. The seed layer 6 may be deposited on the barrier layer 4 using various sputtering methods, CVD, or electroless deposition or combinations thereof. The seed layer 6 thickness, depending on the substrate 2 topography, may vary from 20 to 1500 A°, and may be discontinuous on the corners of the deep recesses of the substrate 2. After depositing the seed layer 6, a conductive layer 8 (e.g., copper layer) is generally electroplated over the seed layer 6 from a suitable acid or non-acidic plating bath or bath formulation.
In general, the texture of a large portion of the conductive layer 8 is dependent upon the texture of an underneath layer, for example, the seed layer 6. Texture as defined in this application includes, but are not limited to, the crystal orientation (i.e., <111>, <110>), grain size, grain boundary (boundary around a single grain), etc. The texture of the remaining portion of the conductive layer 8 is dependent upon the chemicals in the plating bath and the deposition rate. In other words, if the crystal orientation of the seed layer 6 is formed predominantly in a <111> orientation, then a large portion of the conductive layer 8 will have the same crystal orientation, that being <111>. With that being said, the texture of the seed layer 6 is also dependent upon the texture of the barrier layer 4.
When the plated conductive layer 8 is formed on the seed layer 6, the conductive layer 8 may be epitaxial with the seed layer 6 up to a thickness of about 3000 A° from the top surface of the seed layer 6. However, when the thickness of the conductive layer 8 is above 3000 A°, the texture of the portion of the conductive layer 8 above 3000 A° may be dependent upon the nature of the plating bath.
After depositing the conductive layer 8, particularly when the conductive layer 8 is copper or gold, metallurgical grain recovery and grain growth generally occurs at room temperature. Thus, the grain size of the initially deposited conductive layer is typically about 30 to 100 A°, but can increase in size in the range of 2,000 to 10,000 A° after grain growth at room temperature. The final grain size of the conductive layer 8 is dependent on the seed layer 6 material, the chemistry of the plating bath, and annealing temperature.
The texture of the annealed grains in the conductive layer 8 is often very similar to the texture of the grains of the seed layer 6. Thus, it is very difficult to form grains in the conductive layer 8 that are different in their texture from the grains of the seed layer 6. In addition, it is also difficult to accelerate room temperature grain growth of the conductive layer 8 without changing the texture of the seed layer 6, bath chemistry and/or temperature.
Accordingly, there is a need for a method and apparatus that can disassociate the texture of a plated conductive layer from that of the underneath seed layer. There is also a need for a method and apparatus that accelerates room temperature grain recovery and grain growth. Further, there is a need for a method and apparatus that can form a highly desirable conductive layer while increasing the grain size in the conductive layer.